A frequency locked loop (PLL) is a circuit that generates an output signal synchronized in frequency and phase with an input reference signal. It consists of a phase detector (PD), a voltage-controlled oscillator (VCO), and a loop filter (LF). The PD compares the input and output signals, generating an error signal that adjusts the VCO’s frequency and phase until they match the reference. The LF filters the error signal to stabilize the VCO’s output. PLLs are commonly used in frequency synthesis, clock generation, and signal processing applications.
